Integrated circuit electrically erasable programmable read-only memory (EEPROM) devices are well-known memory devices used for non-volatile information storage.
In operation, EEPROM devices generate a number of signals having a variety of voltages One type of EEPROM device, referred to as a "thick oxide EEPROM", incorporates a three layer polysilicon structure as the individual bit memory element (called a "cell"). The three layers of polysilicon are separated from each other by a layer of oxide such that one polysilicon layer is electrically insulated from the other two. Information is retained in the form of an electric charge stored on this insulated layer, which is also called a "floating gate". To program the EEPROM, that is, to store information on the EEPROM, requires a relatively high voltage (e.g., approximately 25 volts) so that electrons may tunnel across the insulating oxide layer from the programming electrode to the floating gate. To erase information requires a voltage sufficient to force the electrons on the floating gate to tunnel across a second oxide layer to an erase electrode. These high voltages, however, may cause the individual memory cells to be no longer isolated from one another, as they must be in order to accurately store information.
A memory cell is no longer electrically isolated from adjacent cells whenever the voltage applied to the memory cell exceeds the field threshold of the field isolation thick oxide MOS (metal oxide semiconductor) transistors between cells The field threshold is the gate voltage at which these field isolation transistors turn on. When the field isolation MOSFET turns on, the associated EEPROM memory cell is no longer isolated from adjacent cells. It is known that the field threshold is strongly affected by the bias voltage applied to the substrate of the memory cell As an increasingly negative voltage is applied to the substrate, the field threshold increases. Specifically, in a typical thick oxide EEPROM device, the field threshold is approximately ten volts when the substrate bias voltage (V.sub.BB) is zero volts. If the substrate bias is -1 volt, the field threshold rises to about 17 volts. Since thick oxide EEPROM cells require up to 25 volts for accurate programming, a substrate bias voltage of approximately -3 volts is required to maintain a field threshold above 25 volts in order to have fully independent non-volatile operation of adjacent cells.
In other words, programming an EEPROM requires approximately 25 volts. To ensure isolation of the individual memory cells requires that the programming voltage remain below the field threshold of parasitic transistors. Thus, the field threshold must be of the order of 25 volts and above. To raise the field threshold to that level requires a negative substrate bias voltage of approximately -3 volts. This substrate bias voltage must be maintained while generally minimizing current consumption.
Charge, however, may leak from the substrate through its p-n junctions with the other layers, causing V.sub.BB to change to a less negative value. Substrate leakage current is more significant with the larger die sizes of modern EEPROMs. Substrate leakage is also higher at high temperature at the high voltages required for EEPROM programming.
Further, whenever high voltage tunneling operations are performed on an EEPROM, the gates, sources, and drains of many transistors in the chip are taken to high voltages Since the gates of these transistors form the top electrode of gate oxide capacitors to the substrate, and the sources and drains form junction capacitors to the substrate, there is substantial capacitive coupling of these high voltages on the gates to the substrate. This results in significant variations in the substrate bias voltage which must be controlled in order to successfully program or erase the EEPROM cell.
Further, certain applications of integrated circuit devices must reliably withstand high ambient temperatures. For example, military specifications require high reliability at relatively higher temperatures.
A further desirable attribute of all electronic devices is low current consumption. Low current usage is particularly important where the devices are battery operated. In addition, the less current required, the smaller and lighter the power source may be. Thus, the minimization of current consumption by the EEPROMs will help to maximize their usefulness. One method of minimizing current is to maintain a low standby current just sufficient to maintain the substrate bias voltage until the next active operation.
There are two approaches taken in the prior art to address the problem of substrate bias voltage leakage.
One prior art approach is to utilize two charge pumps to provide charge to create the substrate voltage. The first pump is a high-frequency, fast charge pump for the active mode of programming or erasing. The second pump is a low-frequency, slow charge pump for the standby mode where the chip is inactive, but the substrate bias voltage must still be maintained. The disadvantages of the two-pump system are that (1) the slow pump tends to consume more current than is needed at the normally low temperatures of the standby mode, thus exacerbating the current consumption problem, and (2) the slow pump is inefficient and, at worst, too weak to maintain the substrate bias voltage at higher temperatures which may exist just after an active to standby transition occurs. Thus the two-pump system is inefficient in that it requires more current than necessary in standby mode and may not be able to supply enough charge at higher temperatures.
Another prior art approach to maintaining the substrate bias voltage is to use a sensor to monitor the V.sub.BB level and turn an oscillator on and off which turns a charge pump on and off as needed to maintain the substrate bias voltage. This system, however, may cause the substrate bias voltage to oscillate in a sawtooth wave fashion. This is because of the lag (hysteresis) of the sensor in its response and the possible overshooting of the pump when turning off. The sawtooth oscillation of the substrate bias voltage creates problems in maintaining the field threshold voltage, thereby presenting problems in isolating the memory cells. The sawtooth oscillation also causes additional noise problems in the circuits because many circuits are capacitively coupled to the substrate bias voltage.
Accordingly, it is an object of the present invention to provide a means for generating and regulating a stable substrate bias voltage for EEPROM and other integrated circuit devices.
It is a further object of the present invention to maintain the stable bias voltage of EEPROM devices at high operating temperatures and during active-to-standby transitions.
It is another object of the present invention to provide a substrate bias voltage generating and regulating circuit which minimizes current consumption.
It is yet another object of the present invention to provide a substrate bias voltage generating and regulating circuit which is a self-contained unit conveniently applicable to existing integrated circuit EEPROMs and other devices.
It is still another object of the present invention to provide a substrate bias voltage generating and regulating circuit which is capable of supplying the substrate current necessary to maintain the desired substrate bias voltage at the relatively high ambient temperatures required to meet military specifications and which also does not consume excessive current at the relatively low ambient temperatures which are also required to meet military specifications.
These and other objects of the present invention will become obvious to those skilled in the art from the following detailed description of the invention and the accompanying drawings.